Details
Title
LAP
Formal Name (French)
Laboratoire d'architecture de processeurs
Formal Name (English)
Processor Architecture Laboratory
Lab Manager
Ienne, Paolo
Group ID
U10418
Affiliated authors
Aminian, Mahdi
Asiatici, Mikhail
Atasu, Kubilay
Athanasopoulos, Panagiotis
Bayrak, Ali Galip
Becker, Andrew James
Beuchat, René
Blanusa, Jovan
Buret, Rodolphe
Cevrero, Alessandro
Coulon, Louis
Elakhras, Ayatallah
Ewaida, Mohsen A A
Fasthuber, Robert
Favi, Claudio
George, Nithin
Gueissaz, Stuart
Guerrieri, Andrea
Ienne, Paolo
Jimenez, Xavier
Josipovic, Lana
Kashani, Sahand
Kluter, Ties Jan Henderikus
Lortkipanidze, Manana
Mata Pavia, Juan
Mester, Christian
Nicoud, Jean-Daniel
Nikolic, Stefan
Novo Bruna, David
Parandeh Afshar, Hadi
Petkovska, Ana
Piguet, Christian
Pozzi, Laura
Purnaprajna, Madhura
Radi, Gianluca
Ramirez, Lucas
Schneeberger, Chantal
Shahawy, Mohamed Mahfouz
Skerlj, Maurizio
Sprenger, Iacopo
Sönmez, Canberk
Velickovic, Nikola
Verma, Ajay Kumar
Vuletic, Miljan
Worm, Frédéric
Zgheib, Grace
Asiatici, Mikhail
Atasu, Kubilay
Athanasopoulos, Panagiotis
Bayrak, Ali Galip
Becker, Andrew James
Beuchat, René
Blanusa, Jovan
Buret, Rodolphe
Cevrero, Alessandro
Coulon, Louis
Elakhras, Ayatallah
Ewaida, Mohsen A A
Fasthuber, Robert
Favi, Claudio
George, Nithin
Gueissaz, Stuart
Guerrieri, Andrea
Ienne, Paolo
Jimenez, Xavier
Josipovic, Lana
Kashani, Sahand
Kluter, Ties Jan Henderikus
Lortkipanidze, Manana
Mata Pavia, Juan
Mester, Christian
Nicoud, Jean-Daniel
Nikolic, Stefan
Novo Bruna, David
Parandeh Afshar, Hadi
Petkovska, Ana
Piguet, Christian
Pozzi, Laura
Purnaprajna, Madhura
Radi, Gianluca
Ramirez, Lucas
Schneeberger, Chantal
Shahawy, Mohamed Mahfouz
Skerlj, Maurizio
Sprenger, Iacopo
Sönmez, Canberk
Velickovic, Nikola
Verma, Ajay Kumar
Vuletic, Miljan
Worm, Frédéric
Zgheib, Grace
Institute
IINFCOM
Faculty
IC
Note
Members of LAP-unit
Linked resource
http://lap.epfl.ch/
Publications
A (Nearly) Free Lunch
Buffer Placement and Sizing for High-Performance Dataflow Circuits
Combining Dynamic & Static Scheduling in High-level Synthesis
Design Space Exploration for Field Programmable Compressor Trees
DynaBurst: Dynamically Assemblying DRAM Bursts over a Multitude of Random Accesses
Heuristic NPN classification for large functions using AIGs and LEXSAT
Introduction: Special Section on Architecture of Future Many Core Systems
Introduction: Special Section on Computer Arithmetic
Satisfiability-Based Methods for Digital Circuit Design, Debug, and Optimization
Variable latency speculative addition: A new paradigm for arithmetic circuit design
See complete list of publications (250)
Buffer Placement and Sizing for High-Performance Dataflow Circuits
Combining Dynamic & Static Scheduling in High-level Synthesis
Design Space Exploration for Field Programmable Compressor Trees
DynaBurst: Dynamically Assemblying DRAM Bursts over a Multitude of Random Accesses
Heuristic NPN classification for large functions using AIGs and LEXSAT
Introduction: Special Section on Architecture of Future Many Core Systems
Introduction: Special Section on Computer Arithmetic
Satisfiability-Based Methods for Digital Circuit Design, Debug, and Optimization
Variable latency speculative addition: A new paradigm for arithmetic circuit design
See complete list of publications (250)
Record appears in
Authorities > Lab