Details
Title
Novo Bruna, David
Sciper ID
196721
Affiliated labs
LAP
Publications
A technology mapper for depth-constrained FPGA logic cells
Automatic support for multi-module parallelism from computational patterns
FPRESSO: Enabling Express Transistor-Level Exploration of FPGA Architectures
Fast Design Space Exploration Using Vivado HLS: Non-binary LDPC Decoders
From low-architectural expertise up to high-throughput non-binary LDPC decoders: Optimization guidelines using high-level synthesis
FudgeFactor: Syntax-Guided Synthesis for Accurate RTL Error Localization and Correction
Improved carry chain mapping for the VTR flow
Non-LUT field-programmable gate arrays
Shortening design time through multiplatform simulations with a portable OpenCL golden-model: the LDPC decoder case
Automatic support for multi-module parallelism from computational patterns
FPRESSO: Enabling Express Transistor-Level Exploration of FPGA Architectures
Fast Design Space Exploration Using Vivado HLS: Non-binary LDPC Decoders
From low-architectural expertise up to high-throughput non-binary LDPC decoders: Optimization guidelines using high-level synthesis
FudgeFactor: Syntax-Guided Synthesis for Accurate RTL Error Localization and Correction
Improved carry chain mapping for the VTR flow
Non-LUT field-programmable gate arrays
Shortening design time through multiplatform simulations with a portable OpenCL golden-model: the LDPC decoder case
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