Details
Title
George, Nithin
Sciper ID
191499
Affiliated labs
LAP
Publications
Automatic support for multi-module parallelism from computational patterns
Design Space Exploration of LDPC Decoders Using High-Level Synthesis
Designing a Virtual Runtime for FPGA Accelerators in the Cloud
Enriching C-based High-Level Synthesis with parallel pattern templates
FPGAs for the Masses: Affordable Hardware Synthesis from Domain-Specific Languages
Fast Design Space Exploration Using Vivado HLS: Non-binary LDPC Decoders
From low-architectural expertise up to high-throughput non-binary LDPC decoders: Optimization guidelines using high-level synthesis
Virtualized Execution Runtime for FPGA Accelerators in the Cloud
Design Space Exploration of LDPC Decoders Using High-Level Synthesis
Designing a Virtual Runtime for FPGA Accelerators in the Cloud
Enriching C-based High-Level Synthesis with parallel pattern templates
FPGAs for the Masses: Affordable Hardware Synthesis from Domain-Specific Languages
Fast Design Space Exploration Using Vivado HLS: Non-binary LDPC Decoders
From low-architectural expertise up to high-throughput non-binary LDPC decoders: Optimization guidelines using high-level synthesis
Virtualized Execution Runtime for FPGA Accelerators in the Cloud
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