Details
Title
Cevrero, Alessandro
Sciper ID
176546
Publications
3D configuration caching for 2D FPGAs
A 64Gb/s 1.4pJ/b NRZ Optical-Receiver Data-Path in 14nm CMOS FinFET
A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions
Design and Analysis of Jitter-Aware Low-Power and High-Speed TSV Links for 3D ICs
Design and Feasibility of Multi-Gb/s Quasi-Serial Vertical Interconnects based on TSVs for 3D ICs
Fast and Accurate BER Estimation Methodology for I/O Links based on Extreme Value Theory
Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs
Generalized programmable counter arrays
Low Power 3D Serial TSV Link for High Bandwidth Cross-Chip Communication
Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver
See complete list of publications (29)
A 64Gb/s 1.4pJ/b NRZ Optical-Receiver Data-Path in 14nm CMOS FinFET
A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions
Design and Analysis of Jitter-Aware Low-Power and High-Speed TSV Links for 3D ICs
Design and Feasibility of Multi-Gb/s Quasi-Serial Vertical Interconnects based on TSVs for 3D ICs
Fast and Accurate BER Estimation Methodology for I/O Links based on Extreme Value Theory
Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs
Generalized programmable counter arrays
Low Power 3D Serial TSV Link for High Bandwidth Cross-Chip Communication
Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver
See complete list of publications (29)
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Cevrero, A
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