The application of Phasor Measurement Units (PMUs) to the real-time monitoring, protection and control of Distribution Networks, requires the availability of high accuracy devices that are characterized at the same time by a reasonable cost. This paper presents the design of a low-cost PMU prototype based on a Field Programmable Gate Array (FPGA) that integrates a recently published synchrophasor estimation technique, called iterative-Interpolated DFT (i-IpDFT). The adopted hardware platform is first introduced, then the major FPGA components are described and integrated in the overall board design. Finally, the performance of the developed prototype is evaluated in terms of the latency of the various PMU components and the scalability of the overall design.