conference paper not in proceedings
Rethinking IOMMU for Future IO Devices
March 30, 2025
IO address translation has become a roadblock for high-speed IO devices to saturate their maximum bandwidth, as the aggregated IO working set can easily exceed the IOTLB coverage, leading to performance overhead of IO page table walks. Inspired by recent core-side virtual memory approaches that lower the OS-level virtual memory areas (VMAs) into hardware to solve the TLB coverage problem, we propose to introduce VMAs into IO address translation with a VMA-granule centralized translation caching design that can achieve both higher performance and stronger security guarantees.
Type
conference paper not in proceedings
Author(s)
EPFL
EPFL
Etsion, Yoav
Yale University
Basu, Arkaprava
EPFL
EPFL
EPFL
Date Issued
2025-03-30
Written at
EPFL
EPFL units
Event name | Event acronym | Event place | Event date |
ASPLOS '25 | Rotterdam, The Netherlands | 2025-03-30 - 2025-04-03 | |
Available on Infoscience
August 25, 2025
Use this identifier to reference this record