IO address translation has become a roadblock for high-speed IO devices to saturate their maximum bandwidth, as the aggregated IO working set can easily exceed the IOTLB coverage, leading to performance overhead of IO page table walks. Inspired by recent core-side virtual memory approaches that lower the OS-level virtual memory areas (VMAs) into hardware to solve the TLB coverage problem, we propose to introduce VMAs into IO address translation with a VMA-granule centralized translation caching design that can achieve both higher performance and stronger security guarantees.