Repository logo

Infoscience

  • English
  • French
Log In
Logo EPFL, École polytechnique fédérale de Lausanne

Infoscience

  • English
  • French
Log In
  1. Home
  2. Academic and Research Output
  3. Journal articles
  4. Reducing the number of comparators in multi-bit ΔΣ modulators
 
research article

Reducing the number of comparators in multi-bit ΔΣ modulators

Pesenti, S.
•
Clément, P.
•
Kayal, M.  
2008
IEEE Transactions on Circuits and Systems I: Regular Papers

Multi-bit feedback, being one way of lowering ΔΣ modulators power consumption, has a major obstacle: the number of components in the internal analog-to-digital converter (ADC) and digital-to-analog converter (DAC). Nevertheless, the number of comparators in the ADC can be significantly reduced depending on the order of noise-shaping and the oversampling ratio. In this paper, we propose an auto-ranging algorithm with a mechanism to keep the structure stable that emulates more quantization levels than that allowed by the number of comparators. As the recourse to segmented DACs allows lowering the complexity of the mismatch shaping encoder, the auto-ranging ADC brings the benefits of multibit feedback without the usual increase in size and power consumption. The internal number of bits in Δ Σ modulators is no more restricted by the difficulty of building the flash ADC with a low voltage supply. © 2008 IEEE.

  • Details
  • Metrics
Logo EPFL, École polytechnique fédérale de Lausanne
  • Contact
  • infoscience@epfl.ch

  • Follow us on Facebook
  • Follow us on Instagram
  • Follow us on LinkedIn
  • Follow us on X
  • Follow us on Youtube
AccessibilityLegal noticePrivacy policyCookie settingsEnd User AgreementGet helpFeedback

Infoscience is a service managed and provided by the Library and IT Services of EPFL. © EPFL, tous droits réservés