Reducing the number of comparators in multi-bit ΔΣ modulators
Multi-bit feedback, being one way of lowering ΔΣ modulators power consumption, has a major obstacle: the number of components in the internal analog-to-digital converter (ADC) and digital-to-analog converter (DAC). Nevertheless, the number of comparators in the ADC can be significantly reduced depending on the order of noise-shaping and the oversampling ratio. In this paper, we propose an auto-ranging algorithm with a mechanism to keep the structure stable that emulates more quantization levels than that allowed by the number of comparators. As the recourse to segmented DACs allows lowering the complexity of the mismatch shaping encoder, the auto-ranging ADC brings the benefits of multibit feedback without the usual increase in size and power consumption. The internal number of bits in Δ Σ modulators is no more restricted by the difficulty of building the flash ADC with a low voltage supply. © 2008 IEEE.
WOS:000256258400005
2-s2.0-44949094677
2008
55
4
1011
1022
Marvell Switzerland Srl, CH-1163 Etoy, Switzerland Electronics Laboratory (LEG), Swiss Federal Institute of Technology (EPFL), CH-1015 Lausanne, Switzerland
Cited By (since 1996): 1
Export Date: 19 January 2010
Source: Scopus
References: Geerts, Y., Steyaert, M., Sansen, W., (2002) Design of multi-bit Delta-Sigma A/D converters, , Boston: Kluwer Academic Publishers; Fishov, A., Siracusa, E., Welz, J., Fogleman, E., Galton, I., Segmented mismatch-shaping D/A conversion (2002) Proc. of the IEEE Intl. Sym. on Circuits and Sys, 4, pp. 679-682. , may; Lu, X., A novel signal-predicting multibit delta-sigma modulator (2004) Proc. of the IEEE Intl. Conf. on Electronics, Circuits and Sys, pp. 105-108. , dec; L. Dorrer, F. Kuttner, P. Greco, P. Torta, and T. Hartig, A 3-mW 74-dB SNR 2-MHz continuous-time Delta-Sigma ADC with a tracking ADC quantizer in 0.13-um CMOS, 40, pp. 2416-2426, December 2005Zierhofer, C.M., Adaptive Sigma-Delta modulation with one-bit quantization (2000) IEEE Trans. on circuits and sys. II, pp. 408-415. , may; Norsworthy, S.R., Schreier, R., Temes, G.C., (1997) Delta-Sigma Data Converters: Theory, Design, and Simulation, , New-York: IEEE; Mason, S.J., Zimmermann, H.J., (1960) Electronic circuits, signals, and systems, , New-York: John Wiley; Maeyer, J.D., Rombouts, P., Weyten, L., Efficient multibit quantization in continous-time Δ∑ modulators (2007) IEEE Trans. on circuits and sys. I, pp. 757-767. , april; Pesenti, S., Hybrid continuous-discrete-time multi-bit Delta-Sigma A/D converters with auto-ranging algorithm, (2008), Ph.D. dissertation, Ecole Polytechnique Fédérale de Lausanne, Lausanne, No 3912Pesenti, S., Clement, P., Stefanovic, D., Kayal, M., A low-power strategy for Delta-Sigma modulators (2007) Proc. of the Intl. Conf. on Mixed Design of Integrated Circuits and Sys., MIXDES, pp. 203-208. , june; Razavi, B., (2001) Design of Analog CMOS Integrated Circuits, , New-York: Mc Graw Hill International Edition; Johns, D.A., Martin, K., (1997) Analog Integrated Circuit Design, , New-York: John Wiley & Sons Inc; Pastre, M., Kayal, M., (2006) Methodology for the digital calibration of analog circuits and systems with case studies, , Berlin: Springer; Kostrikin, A.I., (1982) Introduction to Algegra, , Berlin: Springer
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