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conference paper
Clock jitter estimation in noise
2011
IEEE International Symposium of Circuits and Systems (ISCAS)
Clock timing jitter refers to random perturbations in the sampling time in analog-to-digital converters (ADCs). The perturbations are caused by circuit imperfections in the sampling clock. This paper analyzes the effect of sampling clock jitter on the acquired samples in the midst of quantization noise and random Gaussian noise. The paper proposes a method for estimating the jitter for cognitive radio architectures at high sampling rates. The paper also examines the fixed- point implementation of the algorithm and its theoretical performance.
Type
conference paper
Authors
Publication date
2011
Publisher
Published in
IEEE International Symposium of Circuits and Systems (ISCAS)
Start page
1251
End page
1254
Peer reviewed
REVIEWED
EPFL units
Event name | Event place | Event date |
Rio de Janeiro, Brazil | May 15-18, 2011 | |
Available on Infoscience
December 19, 2017
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