Clock timing jitter refers to random perturbations in the sampling time in analog-to-digital converters (ADCs). The perturbations are caused by circuit imperfections in the sampling clock. This paper analyzes the effect of sampling clock jitter on the acquired samples in the midst of quantization noise and random Gaussian noise. The paper proposes a method for estimating the jitter for cognitive radio architectures at high sampling rates. The paper also examines the fixed- point implementation of the algorithm and its theoretical performance.