System and Method for Optimization of Digital Circuits with Timing and Behavior Co-Designed by Introduction and Exploitation of False Paths

A digital circuit including a signal path with a false path, whereby the signal path includes at least 3 logic instances, the digital circuit further including a logic monitoring element for monitoring a part of the digital circuit, and for outputting a cut-back signal in case a determined risk of a full activation of the signal path is detected in the monitoring, wherein the signal path includes a logic cutting selector element as one of the 3 logic instances, the logic cutting selector element to be triggered by at least the cut-back signal to prevent the full activation of the signal path, the logic cutting selector element being configured to switch, the switching either maintaining the signal path itself, or preventing the full activation of the signal path by substituting it for an alternate signal path, thereby inducing the false path.

Other identifiers:
EPO Family ID: 60330758
TTO: 6.1605
Patent number(s):

 Record created 2017-12-01, last modified 2018-01-28

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