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  4. System and Method for Optimization of Digital Circuits with Timing and Behavior Co-Designed by Introduction and Exploitation of False Paths
 
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System and Method for Optimization of Digital Circuits with Timing and Behavior Co-Designed by Introduction and Exploitation of False Paths

Camus, Vincent  
•
Schlachter, Jérémy
•
Enz, Christian  
2017

A digital circuit including a signal path with a false path, whereby the signal path includes at least 3 logic instances, the digital circuit further including a logic monitoring element for monitoring a part of the digital circuit, and for outputting a cut-back signal in case a determined risk of a full activation of the signal path is detected in the monitoring, wherein the signal path includes a logic cutting selector element as one of the 3 logic instances, the logic cutting selector element to be triggered by at least the cut-back signal to prevent the full activation of the signal path, the logic cutting selector element being configured to switch, the switching either maintaining the signal path itself, or preventing the full activation of the signal path by substituting it for an alternate signal path, thereby inducing the false path.

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Type
patent
EPO Family ID

60330758

Author(s)
Camus, Vincent  
Schlachter, Jérémy
Enz, Christian  
Note

Alternative title(s) : (en) System and method for optimization of digital circuits with timing and behavior co-designed by introduction and exploitation of false paths

TTO classification

TTO:6.1605

EPFL units
AVP-R-TTO  
ICLAB  
DOICountry codeKind codeDate issued

US2017337319

US

A1

2017-11-23

Available on Infoscience
December 1, 2017
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/142395
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