Two-Phase Flow Boiling in a Single Layer of Future High-Performance 3D Stacked Computer Chips

The present study focuses on an experimental investigation of two-phase flow boiling in a silicon multi-microchannel evaporator, which emulates a single layer of a 3D stacked computer chip. The micro-evaporator is comprised of 67 parallel channels, each having a 100 x 100 μm2 cross-section area, and separated by 50 μm-wide fins. Two aluminium micro-heaters were sputtered onto the backside of the test section to provide two 0.5 cm2 heated areas in order to simulate the power dissipated by active component in 3D CMOS chips. The experiments were performed with a second identical test section having 50 μm-wide, 100 μm-deep, and 100 μm-long restrictions (micro-orifices) at the inlet of each channel to stabilize the two-phase flow. The goal of this experimental campaign was to perform simultaneous high-speed flow visualization and infra-red measurements of the two-phase flow and heat transfer dynamics across the entire micro-evaporator area. Refrigerants R245fa, R236fa and R1234ze(E) were chosen as the working fluids. The micro-orifices successfully suppressed back flow, eliminated flow instabilities, provided a good flow distribution, and started the boiling process with some flashed vapor. Thermal performance was found to be uniform widthwise using these orifices.

Published in:
2012 13Th Ieee Intersociety Conference On Thermal And Thermomechanical Phenomena In Electronic Systems (Itherm), 597-605
Presented at:
13th IEEE ITHERM Conference, San Diego, California, USA, May 30 - June 1, 2012
New York, Ieee

 Record created 2012-12-12, last modified 2018-01-28

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