Low-power CMOS, analog transient-stability-simulator for a two-machine power-system
Fried, R.; Cherkaoui, R.; Enz, C.
1997

Abstract

This paper presents a low-power analog simulator for the transient stability of a two-machine power system. The simulator is implemented in a standard digital CMOS process. Its building blocks are: sine shaper, transconductor with extended linear range, and parametric current amplifier. All these circuits operate in weak inversion and use the bulk as an active terminal. Simulation time is typically 104 times shorter than the real time simulated phenomena

Details

Title Low-power CMOS, analog transient-stability-simulator for a two-machine power-system
Author(s) Fried, R. ; Cherkaoui, R. ; Enz, C.
Published in Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age. ISCAS '97 (Cat. No.97CH35987)
Volume 1
Pages 137-40
Date 1997
Keywords
DOI https://doi.org/10.1109/ISCAS.1997.608635
Other identifier(s) View record in Web of Science
Laboratories LRE
LSI2
DESL
Record Appears in Scientific production and competences > STI - School of Engineering > IEM - Institut d'Electricité et de Microtechnique > DESL - Distributed Electrical Systems Laboratory - EOS Holding Chair
Scientific production and competences > STI - School of Engineering > IEM - Institut d'Electricité et de Microtechnique > LSI2 - Integrated Systems Laboratory (STI/IC)
Scientific production and competences > STI - School of Engineering > STI Archives > LRE - Power Systems Laboratory
Peer-reviewed publications
Conference Papers
Work produced at EPFL
Published
Record creation date 2007-04-04

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