Multi-ReRAM synapses for artificial neural network training
Metal-oxide-based resistive memory devices (ReRAM) are being actively researched as synaptic elements of neuromorphic co-processors for training deep neural networks (DNNs). However, device-level non-idealities are posing significant challenges. In this work we present a multi-ReRAM-based synaptic architecture with a counter-based arbitration scheme that shows significant promise. We present a 32x2 crossbar array comprising Pt/HfO2/Ti/TiN-based ReRAM devices with multi-level storage capability and bidirectional conductance response. We study the device characteristics in detail and model the conductance response. We show through simulations that an in-situ trained DNN with a multi-ReRAM synaptic architecture can perform handwritten digit classification task with high accuracies, only 2% lower than software simulations using floating point precision, despite the stochasticity, nonlinearity and large conductance change granularity associated with the devices. Moreover, we show that a network can achieve accuracies > 80% even with just binary ReRAM devices with this architecture.
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Boybat, I., Giovinazzo, C., Shahrabi, E., Krawczuk, I., Giannopoulos, J., Piveteau, C., Le Gallo, M., Ricciardi, C., Sebastian, A., Eleftheriou, E., & Leblebici, Y. (2019, January 1). Multi-ReRAM synapses for artificial neural network training. 2019 Ieee International Symposium on Circuits and Systems (Iscas), IEEE International Symposium on Circuits and Systems. IEEE International Symposium on Circuits and Systems (IEEE ISCAS), Sapporo, JAPAN. https://doi.org/10.1109/ISCAS.2019.8702714
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WOS:000483076402180
2019-01-01
New York
978-1-7281-0397-6
IEEE International Symposium on Circuits and Systems
REVIEWED
EPFL
| Event name | Event place | Event date |
Sapporo, JAPAN | May 26-29, 2019 | |