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  4. Multi-ReRAM synapses for artificial neural network training
 
conference paper

Multi-ReRAM synapses for artificial neural network training

Boybat, Irem  
•
Giovinazzo, Cecilia  
•
Shahrabi, Elmira  
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January 1, 2019
2019 Ieee International Symposium On Circuits And Systems (Iscas)
IEEE International Symposium on Circuits and Systems (IEEE ISCAS)

Metal-oxide-based resistive memory devices (ReRAM) are being actively researched as synaptic elements of neuromorphic co-processors for training deep neural networks (DNNs). However, device-level non-idealities are posing significant challenges. In this work we present a multi-ReRAM-based synaptic architecture with a counter-based arbitration scheme that shows significant promise. We present a 32x2 crossbar array comprising Pt/HfO2/Ti/TiN-based ReRAM devices with multi-level storage capability and bidirectional conductance response. We study the device characteristics in detail and model the conductance response. We show through simulations that an in-situ trained DNN with a multi-ReRAM synaptic architecture can perform handwritten digit classification task with high accuracies, only 2% lower than software simulations using floating point precision, despite the stochasticity, nonlinearity and large conductance change granularity associated with the devices. Moreover, we show that a network can achieve accuracies > 80% even with just binary ReRAM devices with this architecture.

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Type
conference paper
DOI
10.1109/ISCAS.2019.8702714
Web of Science ID

WOS:000483076402180

Author(s)
Boybat, Irem  
Giovinazzo, Cecilia  
Shahrabi, Elmira  
Krawczuk, Igor  
Giannopoulos, Jason
Piveteau, Christophe
Le Gallo, Manuel
Ricciardi, Carlo
Sebastian, Abu
Eleftheriou, Evangelos
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Date Issued

2019-01-01

Publisher

IEEE

Publisher place

New York

Published in
2019 Ieee International Symposium On Circuits And Systems (Iscas)
ISBN of the book

978-1-7281-0397-6

Series title/Series vol.

IEEE International Symposium on Circuits and Systems

Subjects

resistive random access memory

•

neuromorphic computing

•

in-memory computing

•

deep neural networks

•

memory

•

device

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
LSM  
LMIS1  
Event nameEvent placeEvent date
IEEE International Symposium on Circuits and Systems (IEEE ISCAS)

Sapporo, JAPAN

May 26-29, 2019

Available on Infoscience
September 19, 2019
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/161265
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