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  4. A Compact DC and AC Model for Circuit Simulation of High Voltage VDMOS Transistor
 
conference paper

A Compact DC and AC Model for Circuit Simulation of High Voltage VDMOS Transistor

Chauhan, Y. S.  
•
Anghel, C.
•
Krummenacher, F.
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2006
IEEE International Symposium on Quality Electronic Design, ISQED 2006
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Type
conference paper
DOI
10.1109/ISQED.2006.7
Web of Science ID

WOS:000237231000021

Author(s)
Chauhan, Y. S.  
•
Anghel, C.
•
Krummenacher, F.
•
Gillon, R.
•
Baguenier, A.
•
Desoete, B.
•
Frere, S.
•
Ionescu, A. M.  
•
Declercq, M.  
Date Issued

2006

Published in
IEEE International Symposium on Quality Electronic Design, ISQED 2006
Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
NANOLAB  
Available on Infoscience
May 16, 2007
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/6966
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