A 58mW 1.2 mm 2 HSDPA Turbo Decoder ASIC in 0.13 μm CMOS
This paper presents the implementation of the 1.2 mm2 HSDPA turbo decoder ASIC in 0.13 mum CMOS achieves a measured maximum frequency of 246 MHz, which translates to a maximum throughput of 20.2 Mb/s at 5.5 iterations. The peak throughput of 10.8 Mb/s required for HSDPA is achieved at 58 mW and an energy efficiency of 0.7 nJ/b/iter. The number of iterations versus input SNR, as determined by the implemented stopping criterion, and corresponding power measurements.
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Benkeser, C., Burg, A., Cupaiuolo, T., & Huang, Q. (2008). A 58mW 1.2 mm 2 HSDPA Turbo Decoder ASIC in 0.13 μm CMOS. 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 264–265. https://doi.org/10.1109/ISSCC.2008.4523158
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WOS:000262328200010
2008
264
265+612
REVIEWED
EPFL
| Event name | Event place | Event date |
San Francisco, CA | Feb 03-07, 2008 | |