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conference paper
Variable delay ripple carry adder with carry chain interrupt detection
2003
Proceedings Of The 2003 Ieee International Symposium On Circuits And Systems
A statistical approach for the area efficient implementation of fast wide operand adders using early termination detection is described and analyzed. It is shown that high throughput can be achieved based on area- and routing-efficient ripple-carry adders with only marginal overhead. They share a low AT-product with Brent-Kung adders but provide designers with totally different area/delay tradeoffs. The circuit does not require full-custom design and fits well into both self-timed and synchronous designs.
Type
conference paper
Web of Science ID
WOS:000184904800029
Authors
Publication date
2003
Published in
Proceedings Of The 2003 Ieee International Symposium On Circuits And Systems
ISBN of the book
0-7803-7761-3
Volume
5
Start page
113
End page
116
Peer reviewed
REVIEWED
EPFL units
Event name | Event place | Event date |
BANGKOK, THAILAND | May 25-28, 2003 | |
Available on Infoscience
June 6, 2011
Use this identifier to reference this record