A circuit-level substrate current model for smart-power ICs
This paper presents a new modeling methodology accounting for generation and propagation of minority carriers that can be used directly in circuit-level simulators in order to estimate coupled parasitic currents. The model is based on a new compact model of basic components (PN junction and resistance) and takes into account minority carriers at the boundary. An equivalent circuit schematic of the substrate is built by identifying these basic elements in the substrate and interconnecting them. Parasitic effects such as bipolar or latch-up result from the continuity of minority carriers guaranteed by the components' model. A structure similar to a half-bridge perturbing sensitive N-well has been simulated. It is composed by four PN junctions connected together by their common P-doped sides. The results are in good agreement with those obtained from physical device simulations. © 2009 IEEE.
WOS:000279630101237
2009
978-142442893-9
978-1-4244-2892-2
3657
3662
Electronic Laboratory (elab.epfl.ch), EPFL, 1015 Lausanne, Switzerland, Export Date: 19 January 2010, Source: Scopus, Art. No.: 5316405, References: Murari, B., Bertotti, F., Vignola, G., (2002) Smart Power ICs, pp. 218-220. , 2nd Edition, pp, Springer-Verlag, Berlin; Schenkel, M., (2003) Substrate Current Effects in Smart Power ICs, , Hartung-Gorre-Verlag, ISBN 3-89649-848-7; Oehmen, J., Olbrich, M., Hedrich, L., Barke, E., Modeling Lateral Parasitic Transistors in Smart Power ICs (2006) IEEE Trans. on Device and Materials Reliability, 6 (3), pp. 408-420. , September; Saez, R., Kayal, M., Declercq, M., Schneider, M., Design guidelines for CMOS current steering logic (1997) Proc. ISCAS'97; Casalta, J.M., Aragons, X., Rubio, A., Substrate Coupling Evaluation in BiCMOS Technology (1997) IEEE Journal of Solid-State Circuits, 32 (4), pp. 568-603. , April; Clement, F.J.R., Zysman, E., Kayal, M., Declercq, M., Toward a global solution for parasitic coupling modeling and visualization (1994) Custom Integrated Circuits Conference, pp. 537-540. , LAYIN; Birrer, P., Fiez, T.S., Mayaram, K., (2004) Silencer!: A tool for substrate noise coupling analysis, SOC Conference, pp. 105-108; Lo Conte, F., Pastre, M., Sallese, J.M., Krummenacher, F., Kayal, M., (2008) Substrate Current Modeling for High-Voltage Smart Power BCD Technology, IEEE NEWCAST-TAISA, pp. 141-144. , June; Sze, S.M., (1981) Physics of Semiconductor Device, , 2nd Edition, Wiley
REVIEWED
EPFL
| Event name | Event place | Event date |
San Jose, CA, USA | September 20-24, 2009 | |