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  4. A Reconfigurable High-Dynamic Range ∆Σ Front-End with Event-Based Decimation for Bandwidth-Efficient Implantable Neural Interfaces
 
conference paper

A Reconfigurable High-Dynamic Range ∆Σ Front-End with Event-Based Decimation for Bandwidth-Efficient Implantable Neural Interfaces

Martínez, Natalia
•
Sapriza, Juan  
•
Schiavone, Davide  
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May 25, 2025
2025 IEEE International Symposium on Circuits and Systems (ISCAS)
2025 IEEE International Symposium on Circuits and Systems (ISCAS)

As the demand for high channel counts and high-resolution recordings of neural activity continues to grow, the increased power and data rate generated impose hard constraints on the telemetry capabilities of wireless implantable neural interfaces. To address this challenge, this work presents a novel system architecture for a reconfigurable readout circuit. It provides per-channel data rate reduction and adaptable bandwidth to match the characteristics and evolution of the neural signals under non-ideal electrode-tissue interactions. The system consists of a 14-bit hybrid continuous-time/discrete-time delta-sigma (CT/DT-∆Σ) analog front-end (AFE) followed by event-based decimation (EBD) which exploits the inherent sparsity in neural signals. The proposed AFE and EBD co-design was simulated using artifact-laden nonhuman primate microwire recordings. Results demonstrate a dynamic range of 76 dB, ensuring artifact robustness, along with up to a two-order-of-magnitude reduction in output data rate and power-area decimation footprint per channel, offering flexibility for high-quality (14 dB NRMSE) and medium-quality (8 dB NRMSE) reconstructions, based on the characteristics of the neural signals recorded at each channel.

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Type
conference paper
DOI
10.1109/iscas56072.2025.11044062
Author(s)
Martínez, Natalia
Sapriza, Juan  

École Polytechnique Fédérale de Lausanne

Schiavone, Davide  

École Polytechnique Fédérale de Lausanne

Ansaloni, Giovanni  

École Polytechnique Fédérale de Lausanne

Bashford, Luke
Jackson, Andrew
Atienza, David  

École Polytechnique Fédérale de Lausanne

Constandinou, Timothy G.
Date Issued

2025-05-25

Publisher

IEEE

Publisher place

Piscataway, NJ

Published in
2025 IEEE International Symposium on Circuits and Systems (ISCAS)
DOI of the book
https://doi.org/10.1109/ISCAS56072.2025
ISBN of the book

979-8-3503-5683-0

Start page

1

End page

5

Subjects

Implantable neural interfaces

•

neural recording

•

delta-sigma

•

event-based compression

•

brain-computer interfaces

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
ESL  
Event nameEvent acronymEvent placeEvent date
2025 IEEE International Symposium on Circuits and Systems (ISCAS)

ISCAS 2025

London, United Kingdom

2025-05-25 - 2025-05-28

Available on Infoscience
July 1, 2025
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/251796
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