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  4. Modified Joint Channel-and-Data Estimation for One-Bit Massive MIMO
 
conference paper

Modified Joint Channel-and-Data Estimation for One-Bit Massive MIMO

Bahari, Mohammadhossein  
•
Rasoulinezhad, Seyedramin
•
Amiri, Mahdi
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January 1, 2021
2021 Ieee International Symposium On Circuits And Systems (Iscas)
IEEE International Symposium on Circuits and Systems (IEEE ISCAS)

Centralized and cloud computing-based network architectures are the promising tracks of future communication systems where a large scale compute power can be virtualized for various algorithms. These architectures rely on high-performance communication links between the base stations and the central computing systems. On the other hand, massive Multiple-Input Multiple-Output (MIMO) technology is a promising solution for base stations toward higher spectral efficiency. To reduce system complexity and energy consumption, 1-bit analog-to-digital converters (ADCs) are leveraged with the cost of lowering the signal quality. To recover the lost information, more sophisticated algorithms, like Joint Channel-and-Data (JCD) estimation, are required whose computation demand is a barrier toward practical implementation. In this paper, we suggest modifications to the current state-of-the-art JCD estimation algorithm to enhance its performance and ease the implementation costs. The modified algorithm delivers up to 4 dB higher symbol error rate in high SNR cases. This improvement is based on a new initialization strategy and an efficient exit condition with lower computation time. We implemented the proposed algorithm on a GPU accelerated system with higher throughput compared to the vanilla BiG-AMP algorithm suitable for software-defined radio systems. To the best of our knowledge, it is the first practical implementation of 1-bit JCD estimation for massive MIMO systems.

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Type
conference paper
DOI
10.1109/ISCAS51556.2021.9401552
Web of Science ID

WOS:000706507900075

Author(s)
Bahari, Mohammadhossein  
Rasoulinezhad, Seyedramin
Amiri, Mahdi
Gilani, Farzam
Saadatnejad, Saeed  
Nezamalhosseini, Seyed Alireza
Shabany, Mahdi
Date Issued

2021-01-01

Publisher

IEEE

Publisher place

New York

Published in
2021 Ieee International Symposium On Circuits And Systems (Iscas)
ISBN of the book

978-1-7281-9201-7

Series title/Series vol.

IEEE International Symposium on Circuits and Systems

Subjects

Engineering, Electrical & Electronic

•

Engineering

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
VITA  
Event nameEvent placeEvent date
IEEE International Symposium on Circuits and Systems (IEEE ISCAS)

Daegu, SOUTH KOREA

May 22-28, 2021

Available on Infoscience
November 20, 2021
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/183139
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