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  4. Efficient Dynamic Optimisation Heuristics for Dataflow Pipelines
 
conference paper

Efficient Dynamic Optimisation Heuristics for Dataflow Pipelines

Prihozhy, A.  
•
Casale-Brunet, S.  
•
Bezati, E.  
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January 1, 2018
Proceedings Of The 2018 Ieee International Workshop On Signal Processing Systems (Sips)
IEEE International Workshop on Signal Processing Systems (IEEE SiPS)

Large dataflow designs appear as a result of functional specification of modern complex digital systems and/ or a result of unfolding and behavioral transformation of looped and branched programs. Since deep-submicron silicon technology provides large amounts of available resources, pipelining optimization without resource sharing can give significant advantages in performance. In this work, we propose a novel pipeline optimization heuristic algorithm, which is named HADD. It is suitable for very large dataflow programs and makes use of efficient dynamic heuristics and a random search on the set of solutions. For a pipeline-stage time-period, it quickly minimizes the number of stages and successively finds the assignment of operators to stages with the objective of minimizing the overall pipeline registers size. The experimental results show that HADD gives solutions that are very close to accurate solutions with only 2% of the difference and overcomes by about 10% on average the best-known heuristic technique HT, which uses mixed static-dynamic heuristics on large designs. Moreover, HADD is c. a. 10 times faster on average against HT.

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Type
conference paper
DOI
10.1109/SiPS.2018.8598386
Web of Science ID

WOS:000465106800058

Author(s)
Prihozhy, A.  
Casale-Brunet, S.  
Bezati, E.  
Mattavelli, M.  
Date Issued

2018-01-01

Publisher

IEEE

Publisher place

New York

Published in
Proceedings Of The 2018 Ieee International Workshop On Signal Processing Systems (Sips)
ISBN of the book

978-1-5386-6318-9

Series title/Series vol.

IEEE Workshop on Signal Processing Systems

Start page

337

End page

342

Subjects

Engineering, Electrical & Electronic

•

Engineering

•

pipeline

•

data flow

•

high level synthesis

•

dynamic heuristics

•

optimization

•

exploration

•

selection

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
SCI-STI-MM  
VLSC  
Event nameEvent placeEvent date
IEEE International Workshop on Signal Processing Systems (IEEE SiPS)

Cape Town, SOUTH AFRICA

Oct 21-24, 2018

Available on Infoscience
June 18, 2019
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/157519
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