In order for any non-volatile memory (NVM) to be considered a viable technology, its reliability should be verified at the array level. In particular, properties such as high endurance and at least moderate data retention are considered essential. Phase-change memory (PCM) is one such NVM technology that possesses highly desirable features and has reached an advanced level of maturity through intensive research and development in the past decade. Multilevel-cell (MLC) capability, i.e., storage of two bits per cell or more, is not only desirable as it reduces the effective cost per storage capacity, but a necessary feature for the competitiveness of PCM against the incumbent technologies, namely DRAM and Flash memory. MLC storage in PCM, however, is seriously challenged by phenomena such as cell variability, intrinsic noise, and resistance drift. We present a collection of advanced circuit-level solutions to the above challenges, and demonstrate the viability of MLC PCM at the array level. Notably, we demonstrate reliable storage and moderate data retention of 2 bits/cell PCM, on a 64 k cell array, at elevated temperatures and after 1 million SET/RESET endurance cycles. Under similar operating conditions, we also show feasibility of 3 bits/cell PCM, for the first time ever.