Repository logo

Infoscience

  • English
  • French
Log In
Logo EPFL, École polytechnique fédérale de Lausanne

Infoscience

  • English
  • French
Log In
  1. Home
  2. Academic and Research Output
  3. Journal articles
  4. A Synchronization-Based Hybrid-Memory Multi-Core Architecture for Energy-Efficient Biomedical Signal Processing
 
research article

A Synchronization-Based Hybrid-Memory Multi-Core Architecture for Energy-Efficient Biomedical Signal Processing

Braojos Lopez, Ruben  
•
Bortolotti, Daniele
•
Bartolini, Andrea
Show more
2017
IEEE Transactions on Computers

In the last decade, improvements on technology scaling have enabled the design of a novel generation of wearable bio-sensing monitors. These smart Wireless Body Sensor Nodes (WBSNs) are able to acquire and process biological signals, such as electrocardiograms, for periods of time extending from hours to days. The energy required for the on-node digital signal processing (DSP) is a crucial limiting factor in the conception of these devices. To address this design challenge, we introduce a domain-specific ultra-low power (ULP) architecture dedicated to bio-signal processing. The platform features a light-weight strategy to support different operating modes and synchronization among cores. Our approach effectively reduces the power consumption, harnessing the intrinsic parallelism and the workload requirements characterizing the target domain. Operations at low voltage levels are supported by a heterogeneous memory subsystem comprising a standard-cell based ultra-low voltage reliable partition. Experimental results show that, when executing real-world bio-signal DSP applications, a state-of-the-art multi-core architecture can improve its energy efficiency in up to 50% by utilizing our proposed approach, outperforming traditional single-core alternatives.

  • Files
  • Details
  • Metrics
Type
research article
DOI
10.1109/TC.2016.2610426
Web of Science ID

WOS:000397632300002

Author(s)
Braojos Lopez, Ruben  
Bortolotti, Daniele
Bartolini, Andrea
Ansaloni, Giovanni  
Benini, Luca
Atienza, David  
Date Issued

2017

Publisher

Institute of Electrical and Electronics Engineers

Published in
IEEE Transactions on Computers
Volume

66

Issue

4

Start page

575

End page

585

Subjects

Biomedical Signal Processing

•

WBSN

•

Low-Power Architectures

•

Reliable Heterogeneous Memory

•

Code Synchronization

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
ESL  
Available on Infoscience
November 8, 2016
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/130963
Logo EPFL, École polytechnique fédérale de Lausanne
  • Contact
  • infoscience@epfl.ch

  • Follow us on Facebook
  • Follow us on Instagram
  • Follow us on LinkedIn
  • Follow us on X
  • Follow us on Youtube
AccessibilityLegal noticePrivacy policyCookie settingsEnd User AgreementGet helpFeedback

Infoscience is a service managed and provided by the Library and IT Services of EPFL. © EPFL, tous droits réservés