The topological (asymmetry) offset voltage of CMOS cross-like Hall cells is analyzed in this paper. In order to attain the stated objective, different approaches have been considered. Both circuit and three-dimensional models have been developed. Variation of the misalignment offset with the biasing current has been studied through physical and circuit models. The latter is a non-homogenous finite elements model, which relies on using parameterized resistances and current-controlled current sources, of CMOS Hall cells. The displacement offset for various asymmetries and the offset variation with the temperature were investigated through the circuit model developed. Various experimental results for the single and magnetic equivalent offset have also been provided.