research article
Synthesizing Hardware from Dataflow Programs
The MPEG Reconfigurable Video Coding working group is developing a new library-based process for building the reference codecs of future MPEG standards, which is based on dataflow and uses an actor language called Cal. The paper presents a code generator producing RTL targeting FPGAs for Cal, outlines its structure, and demonstrates its performance on an MPEG-4 Simple Profile decoder. The resulting implementation is smaller and faster than a comparable RTL reference design, and the second half of the paper discusses some of the reasons for this counter-intuitive result.
Type
research article
Web of Science ID
WOS:000289110100007
Author(s)
Date Issued
2011
Published in
Volume
63
Start page
241
End page
249
Subjects
Editorial or Peer reviewed
REVIEWED
Written at
EPFL
EPFL units
Available on Infoscience
January 21, 2010
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