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research article

Synthesizing Hardware from Dataflow Programs

Janneck, Jörn W.
•
Miller, Ian D.
•
Parlour, David B.
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2011
Journal of Signal Processing Systems

The MPEG Reconfigurable Video Coding working group is developing a new library-based process for building the reference codecs of future MPEG standards, which is based on dataflow and uses an actor language called Cal. The paper presents a code generator producing RTL targeting FPGAs for Cal, outlines its structure, and demonstrates its performance on an MPEG-4 Simple Profile decoder. The resulting implementation is smaller and faster than a comparable RTL reference design, and the second half of the paper discusses some of the reasons for this counter-intuitive result.

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Type
research article
DOI
10.1007/s11265-009-0397-5
Web of Science ID

WOS:000289110100007

Author(s)
Janneck, Jörn W.
Miller, Ian D.
Parlour, David B.
Roquier, Ghislain  
Wipliez, Matthieu
Raulet, Mickaël
Date Issued

2011

Published in
Journal of Signal Processing Systems
Volume

63

Start page

241

End page

249

Subjects

Dataflow

•

Cal

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Reconfigurable Video Coding

•

MPEG

•

High-level synthesis

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
SCI-STI-MM  
Available on Infoscience
January 21, 2010
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/45755
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