In this paper we report the fabrication and detailed electrical characterization of a Metal-Ferroelectric-Oxide-Semiconductor Capacitor aiming at the extraction of the polarization characteristic. In order to evaluate the electrical performances of the ferroelectric over SiO2 capacitor, we propose a simple device test structure featuring an intermediate contact between the two insulators. The investigated test structures are fabricated on highly doped silicon with a gate stack including 40nm silicon dioxide, 100nm Pt intermediate contact, 160nm P(VDF-TrFE) and Au as a top contact. Based on voltage measurements and using an analytical model, we subsequently extract the polarization curves without the need of capacitive measurements. The proposed test structure can serve the future experimental investigation of the possible negative capacitances in complex ferroelectric gate stacks. © 2009 IEEE.