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  4. Low Power and Scalable Many-Core Architecture for Big-Data Stream Computing
 
conference paper

Low Power and Scalable Many-Core Architecture for Big-Data Stream Computing

Kanoun, Karim  
•
Ruggiero, Martino  
•
Atienza Alonso, David  
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2014
Proceedings of the IEEE Annual Symposium on VLSI 2014 (ISVLSI)
IEEE Annual Symposium on VLSI 2014 (ISVLSI)

In the last years the process of examining large amounts of different types of data, or Big-Data, in an effort to uncover hidden patterns or unknown correlations has become a major need in our society. In this context, stream mining applications are now widely used in several domains such as financial analysis, video annotation, surveillance, medical services, traffic prediction, etc. In order to cope with the Big-Data stream input and its high variability, modern stream mining applications implement systems with heterogeneous classifiers and adapt online to its input data stream characteristics variation. Moreover, unlike existing architectures for video processing and compression applications, where the processing units are reconfigurable in terms of parameters and possibly even functions as the input data is changing, in Big-Data stream mining applications the complete computing pipeline is changing, as entirely new classifiers and processing functions are invoked depending on the input stream. As a result, new approaches of reconfigurable hardware platform architectures are needed to handle Big-Data streams. However, hardware solutions that have been proposed so far for stream mining applications either target high performance computing without any power consideration (i.e., limiting their applicability in small-scale computing infrastructures or current embedded systems), or they are simply dedicated to a specific learning algorithm (i.e., limited to run with a single type of classifiers). Therefore, in this paper we propose a novel low-power manycore architecture for stream mining applications that is able to cope with the dynamic data-driven nature of stream mining applications while consuming limited power. Our exploration indicates that this new proposed architecture is able to adapt to different classifiers complexities thanks to its multiple scalable vector processing units and their re-configurability feature at runtime. Moreover, our platform architecture includes a memory hierarchy optimized for Big-Data streaming and implements modern fine-grained power management techniques over all the different types of cores allowing then minimum energy consumption for each type of executed classifier

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Type
conference paper
DOI
10.1109/ISVLSI.2014.77
Author(s)
Kanoun, Karim  
Ruggiero, Martino  
Atienza Alonso, David  
Van Der Schaar, Mihaela
Date Issued

2014

Publisher

IEEE Press

Publisher place

New York

Published in
Proceedings of the IEEE Annual Symposium on VLSI 2014 (ISVLSI)
ISBN of the book

978-1-4799-3765-3/14

Volume

1

Issue

1

Start page

468

End page

473

Subjects

Big Data

•

Stream Computing

•

Many-Core

•

Low Power

•

MPSoC

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
ESL  
Event nameEvent placeEvent date
IEEE Annual Symposium on VLSI 2014 (ISVLSI)

Tampa, Florida, USA

July 9-11, 2014

Available on Infoscience
July 23, 2014
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/105230
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