Technology mapping transforms a technology-independent representation into a technology-dependent one given a library of cells. Even if technology libraries contain multi-output cells, state-of-the-art techniques fully exploit single-output cells only. Multi-output cells have limited support in logic synthesis and are typically handled as white boxes once identified. This paper presents a scalable method to increase the support of multi-output library cells in technology mapping. Our contributions include 1) an approach to detect multi-output cells, 2) a fast Boolean matching methodology, and 3) a technology mapping algorithm that supports multi-output cells. Unlike previous work, we address the mapping problem over the whole network. This has the advantage of optimizing area and delay without requiring many incremental steps. The experiments show that full adders and half adders are efficiently detected and mapped with an average area improvement of 7.48% when mapping for minimal delay compared to the default mapper in ABC. Moreover, our method improves the area of the synthesis flow in Yosys, which treats multi-output cells as white boxes, by 5% on average with a limited run time overhead.