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  4. Double-Gate Pentacene TFTs with Improved Control in Subthreshold Region
 
conference paper

Double-Gate Pentacene TFTs with Improved Control in Subthreshold Region

Cvetkovic, N. V.  
•
Tsamados, D.
•
Sidler, K.  
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2009
Proceedings of the 39th European Solid-State Device Research Conference (ESSDERC)
39th European Solid-State Device Research Conference (ESSDERC)

In this work a double-gate pentacene TFT architecture is presented. The devices are fabricated on a polyimide substrate using three aligned levels of stencil lithography along with standard photolithography, which enable a soft yet well controlled device processing. The benefic impact of the top gate voltage control to reduce the leakage current and significantly improve the subthreshold swing of the device is demonstrated. Moreover, this original design show good promise for the enhancement of Ion/Ioff TEF characteristics.

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Type
conference paper
DOI
10.1109/ESSDERC.2009.5331352
Author(s)
Cvetkovic, N. V.  
Tsamados, D.
Sidler, K.  
Bhandari, J.  
Savu, V.  
Brugger, J.  
Ionescu, A. M.  
Date Issued

2009

Publisher

IEEE

Published in
Proceedings of the 39th European Solid-State Device Research Conference (ESSDERC)
Start page

205

End page

208

Subjects

double-gate

•

pentacene

•

leakage current

•

subthreshold

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
NANOLAB  
LMIS1  
Event nameEvent placeEvent date
39th European Solid-State Device Research Conference (ESSDERC)

Athens, Greece

September 14-18, 2009

Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/42772
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