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  4. A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories
 
conference paper

A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories

Vieira, Joao
•
Giacomin, Edouard
•
Qureshi, Yasir Mahmood  
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October 6, 2019
2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC)
27th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)

The need for running complex Machine Learning (ML) algorithms, such as Convolutional Neural Networks (CNNs), in edge devices, which are highly constrained in terms of computing power and energy, makes it important to execute such applications efficiently. The situation has led to the popularization of Binary Neural Networks (BNNs), which significantly reduce execution time and memory requirements by representing the weights (and possibly the data being operated) using only one bit. Because approximately 90% of the operations executed by CNNs and BNNs are convolutions, a significant part of the memory transfers consists of fetching the convolutional kernels. Such kernels are usually small (e.g., 3×3 operands), and particularly in BNNs redundancy is expected. Therefore, equal kernels can be mapped to the same memory addresses, requiring significantly less memory to store them. In this context, this paper presents a custom Binary Dot Product Engine (BDPE) for BNNs that exploits the features of Resistive Random-Access Memories (RRAMs). This new engine allows accelerating the execution of the inference phase of BNNs. The novel BDPE locally stores the most used binary weights and performs binary convolution using computing capabilities enabled by the RRAMs. The system-level gem5 architectural simulator was used together with a C-based ML framework to evaluate the system’s performance and obtain power results. Results show that this novel BDPE improves performance by 11.3%, energy efficiency by 7.4% and reduces the number of memory accesses by 10.7% at a cost of less than 0.3% additional die area, when integrated with a 28nm Fully Depleted Silicon On Insulator ARMv8 in-order core, in comparison to a fully-optimized baseline of YoloV3 XNOR-Net running in a unmodified Central Processing Unit.

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Type
conference paper
DOI
10.1109/VLSI-SoC.2019.8920343
Author(s)
Vieira, Joao
Giacomin, Edouard
Qureshi, Yasir Mahmood  
Zapater Sancho, Marina  
Tang, Xifan
Kvatinsky, Shahar
Atienza Alonso, David  
Gaillardon, Pierre-Emmanuel
Date Issued

2019-10-06

Published in
2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC)
Total of pages

6

Start page

160

End page

165

Subjects

Machine Learning

•

Edge Devices

•

Binary Neural Networks

•

RRAM-based Binary Dot Product Engine

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
ESL  
Event nameEvent placeEvent date
27th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)

Cuzco, Peru

October 6-9, 2019

Available on Infoscience
June 26, 2019
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/158556
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