Defects in MOSFET oxides are a major issue in CMOS technologies, affecting not only the device electrical performances but also compromising reliability and endurance. Using Charge-Pumping and C-V measurements, defects have been characterized in native and electrically-aged oxides. These electrical measurements have been compared to the predictions of advanced simulations, accounting for multi-phonon assisted emission/capture rates and including the presence of multiple defects and the contribution of electron and holes tunneling from both the gate and the channel. The proposed model allows an accurate description of the dynamics of trap occupation during electrical stress and can be used for the rigorous extraction of trap concentration from CV measurements.