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  4. A 17ps Time-to-digital Converter Implemented in 65nm FPGA Technology
 
conference paper

A 17ps Time-to-digital Converter Implemented in 65nm FPGA Technology

Favi, C.  
•
Charbon, E.  
2009
FPGA '09: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
ISFPGA
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Type
conference paper
DOI
10.1145/1508128.1508145
Author(s)
Favi, C.  
Charbon, E.  
Date Issued

2009

Published in
FPGA '09: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Start page

113

End page

120

Subjects

NCCR-MICS

•

NCCR-MICS/CL2

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
AQUA  
Event nameEvent placeEvent date
ISFPGA

Monterey

2009

Available on Infoscience
July 13, 2009
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/41289
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