Microchannel liquid cooling has been proposed since the late 2000s as a viable enabler for 3D integration of microprocessors to continue scaling of computing power in the face of increasingly reduced returns from CMOS technology scaling. Thermal and electrical demonstrations of microchannel liquid-cooled heat sinks on the back side of IC dies exist in the literature and the compatibility of its fabrication with the existing CMOS process has been shown. This compatibility also gives rise to the prospect of building of nearly an infinite variety of channel networks with no additional manufacturing cost. This ICCAD 2015 problem aims to identify methods to optimize such microchannel fluid networks, and to evaluate impact of different cooling networks on different computing architectures floorplans.