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  4. Improving the power-delay performance in subthreshold source-coupled logic circuits
 
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Improving the power-delay performance in subthreshold source-coupled logic circuits

Tajalli, Armin  
•
Alioto, Massimo
•
Brauer, Elizabeth
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Svensson, Lars
•
Monteiro, Jose
2009
Proceedings of the International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)
International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)

Subthreshold source-coupled logic (STSCL) circuits can be used in design of low-voltage and ultra-low power digital systems. This article introduces and analyzes new techniques for implementing complex digital systems using STSCL gates with an improved power-delay product (PDP) based on source-follower output stages. A test chip has been manufactured in a conventional digital 0.18$\mu$m CMOS technology to evaluate the performance of the proposed STSCL circuit, and speed and PDP improvements by a factor of up to 2.4 were demonstrated.

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2008_PATMOS_STSCLSFB_Tajalli.pdf

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openaccess

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1.36 MB

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3d60e89169ffc0191a8a1017289fbf73

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