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conference paper
Improving the power-delay performance in subthreshold source-coupled logic circuits
Svensson, Lars
•
Monteiro, Jose
2009
Proceedings of the International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)
Subthreshold source-coupled logic (STSCL) circuits can be used in design of low-voltage and ultra-low power digital systems. This article introduces and analyzes new techniques for implementing complex digital systems using STSCL gates with an improved power-delay product (PDP) based on source-follower output stages. A test chip has been manufactured in a conventional digital 0.18$\mu$m CMOS technology to evaluate the performance of the proposed STSCL circuit, and speed and PDP improvements by a factor of up to 2.4 were demonstrated.
Type
conference paper
Web of Science ID
WOS:000264555300003
Author(s)
Editors
Svensson, Lars
•
Monteiro, Jose
Date Issued
2009
Publisher
Published in
Proceedings of the International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)
Series title/Series vol.
Integrated Circuit and System Design
Start page
21
End page
30
Peer reviewed
REVIEWED
Written at
EPFL
EPFL units
| Event name | Event place | Event date |
Lisbon, Portugal | September 10-12 | |
Available on Infoscience
July 10, 2008
Use this identifier to reference this record