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research article

Investigation of Tunnel Field-Effect Transistors as a Capacitor-less Memory Cell

Biswas, Arnab  
•
Dagtekin, Nilay  
•
Grabinski, Wladyslaw  
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2014
Applied Physics Letters

In this work we report experimental results on the use of Tunnel Field-Effect Transistors (TFET) as capacitorless Dynamic Random Access Memory (DRAM) cells, implemented as a double-gate (DG) Fully-Depleted Silicon-On-Insulator (FD-SOI) devices. The devices have an asymmetric design, with a partial overlap of the top gate (LG) with a total overlap of the back gate over the channel region (LG+LIN). A potential well is created by biasing the back gate (VBG) in accumulation while the front gate (VFG) is in inversion. Holes from the p+ source are injected by the forward-biased p+i junction and stored in the electrically induced potential well.

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Type
research article
DOI
10.1063/1.4867527
Web of Science ID

WOS:000332729200045

Author(s)
Biswas, Arnab  
•
Dagtekin, Nilay  
•
Grabinski, Wladyslaw  
•
Bazigos, Antonios  
•
Royer, Cyrille Le
•
Hartmann, Jean-Michel
•
Tabone, Claude
•
Vinet, Maud
•
Ionescu, Mihai Adrian  
Date Issued

2014

Publisher

American Institute of Physics

Published in
Applied Physics Letters
Volume

104

Issue

9

Article Number

092108

Subjects

Tunnel FET

•

Capacitorless memory

•

DRAM

•

1 Transistor memory

Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
NANOLAB  
Available on Infoscience
February 24, 2014
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/101131
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