In modern VLSI circuits, a large number of clock buffers are inserted in clock distribution networks, which are significantly affected by process and power supply noise variations. The combined effect of process variations and power supply noise on clock skew and jitter is investigated in this paper. A statistical model of skew and jitter is proposed. Clock paths with different buffer insertion strategies are compared in terms of skew and jitter. The tradeoffs among the constraints on clock jitter, skew, slew rate, and power are discussed. For strict timing constraints, severe power overhead (> 110%) has to be added to obtain a low improvement in the worst case skitter and slew rate (<13%). The effect of widely-used techniques, such as recombinant trees and dynamic voltage scaling, on decreasing skitter is also investigated.