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  4. Efficient Hashing Using the AES Instruction Set
 
conference paper

Efficient Hashing Using the AES Instruction Set

Bos, Joppe Willem  
•
Özen, Onur  
•
Stam, Martijn  
Preneel, Bart
•
Takagi, Tsuyoshi
2011
Cryptographic Hardware and Embedded Systems – CHES 2011
Cryptographic Hardware and Embedded Systems

In this work, we provide a software benchmark for a large range of 256-bit blockcipher-based hash functions. We instantiate the underlying blockcipher with AES, which allows us to exploit the recent AES instruction set (AESNI). Since AES itself only outputs 128 bits, we consider double-block-length constructions, as well as (single-block-length) constructions based on RIJNDAEL-256. Although we primarily target architectures supporting AES-NI, our framework has much broader applications by estimating the performance of these hash functions on any (micro-)architecture given AES-benchmark results. As far as we are aware, this is the first comprehensive performance comparison of multiblock- length hash functions in software.

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Type
conference paper
DOI
10.1007/978-3-642-23951-9_33
Web of Science ID

WOS:000306714800033

Author(s)
Bos, Joppe Willem  
Özen, Onur  
Stam, Martijn  
Editors
Preneel, Bart
•
Takagi, Tsuyoshi
Date Issued

2011

Publisher

Springer Berlin Heidelberg

Publisher place

Berlin, Heidelberg

Published in
Cryptographic Hardware and Embedded Systems – CHES 2011
ISBN of the book

978-3-642-23950-2

Total of pages

16

Series title/Series vol.

Lecture Notes in Computer Science

Volume

6917

Start page

507

End page

522

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
LACAL  
Event nameEvent placeEvent date
Cryptographic Hardware and Embedded Systems

Nara, Japan

September 28 - October 1, 2011

Available on Infoscience
December 21, 2011
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/75908
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