The floating gate (FG) potential VFG in a non–volatile flash memory (NVM) device is the main parameter controlling the behavior of the cell. A common technique to model VFG is based on the calculation of the coupling coefficients between all the terminals [1]. To this purpose, the capacitance between the control gate (CG) and the FG, separated by an oxide-nitride-oxide (ONO) dielectric layer, must be accurately modeled. In this work a physical model of the ONO capacitance is presented. This model is based on a structuredecomposition approach and on the principle of Gauss law integration along electrical field lines between the CG and the FG [2]. Moreover, most compact models used in industry consider fringing or corner capacitances as fitting parameters, which is not appropriate when technology scalability must be taken into account. The physical–level model presented in this work supports accurate modeling of cell layout scalability as well as process variations.