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conference paper

Classifying Functions with Exact Synthesis

Haaswijk, Winston
•
Testa, Eleonora  
•
Soeken, Mathias  
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May 24, 2017
Proceedings of the 47th International Symposium on Multiple-Valued Logic (ISMVL)
IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL)

Due to recent advances, constraint solvers have become efficient tools for synthesizing optimum Boolean circuits. We take advantage of this by showing how SAT based exact synthesis may be used as a method for finding minimum length Boolean chains. As opposed to other exact synthesis methods, ours may be easily parallelized, which we use to obtain a speedup of approximately 48 times. By combining our method with NPN canonization, we find for the first time the minimum length chains for all 4- and 5-input functions in terms of 3-input Boolean operators. Finally, we propose a hardware acceleration method for NPN canonization. It can be used to speed up NPN canonization in existing algorithms, and we believe it will allow us to find all 6-input NPN classes as well.

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