In this paper, we propose a methodology to evaluate the potential of submicrometer organic thin-film transistors (OTFTs) with nanoimprinted gate and self-aligned source and drain contacts. In the first step, the dedicated static model we previously reported is updated to account for the subthreshold regime and is used to simulate a zero-VGS inverter (one of the most basic unipolar logic gate). Based on the extracted noise margins, two methodologies were studied to assess the potential of this technology in terms of p-logic digital circuits. The first one is De Vusser's VT-based method that we adapted to our OTFT model. The second one relies on statistical modeling and takes into account the actual worst case scenario for an inverter in terms of noise margins. It better represents the experimental distribution because of specific corner models. The different analysis studied in this paper shows that these OTFTs, in the current state of the technology, are still not ready for complex digital circuits as the throughput is expected to be quite low. In addition, the proposed methodology and related interpretation are technology-independent therefore this analysis may serve as a basis to characterize unipolar-logic printed electronics and can be further extended to complementary-logic circuits.