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  4. Temperature-Aware Processor Frequency Assignment for MPSoCs Using Convex Optimization
 
conference paper

Temperature-Aware Processor Frequency Assignment for MPSoCs Using Convex Optimization

Murali, Srinivasan  
•
Mutapcic, Almir
•
Atienza, David  
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2007
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES + ISSS)
International Conference on Hardware/Software Codesign and System Synthesis (CODES + ISSS)

The increasing processing capability of Multi-Processor Systems-on-Chips (MPSoCs) is leading to an increase in chip power dissipation, which in turn leads to significant increase in chip temperature. An important challenge facing the MPSoC designers is to achieve the highest performance system operation that satisfies the temperature and power consumption constraints. The frequency of operation of the different processors and the application workload assignment play a critical role in determining the performance, power consumption and temperature profile of the MPSoC. In this paper, we propose novel convex optimization based methods that solve this important problem of temperature-aware processor frequency assignment, such that the total system performance is maximized and the temperature and power constraints are met. We perform experiments on several realistic SoC benchmarks using a cycle-accurate FPGA-based thermal emulation platform, which show that the systems designed using our methods meet the tem- perature and power consumption requirements at all time instances, while achieving maximum performance.

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Type
conference paper
Author(s)
Murali, Srinivasan  
Mutapcic, Almir
Atienza, David  
Gupta, Rajesh
Boyd, Stephen P.
De Micheli, Giovanni  
Date Issued

2007

Published in
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES + ISSS)
ISBN of the book

978-1-59593-824-4/07/0009

Start page

111

End page

116

Subjects

Temperature-aware

•

Thermal

•

MPSoCs

•

Convex optimization

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
LSI1  
ESL  
Event nameEvent placeEvent date
International Conference on Hardware/Software Codesign and System Synthesis (CODES + ISSS)

Salzburg, Austria

September 30 - October 3, 2007

Available on Infoscience
December 4, 2007
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/15257
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