An Analog to Digital Converter (ADC) using the low duty-cycle nature of pulse-based Ultra Wide-Band (UWB) communications to reduce its power consumption is proposed. Implemented in CMOS 180 nm technology, it can capture a 5 ns window at 4 GS/s each 100 ns, which corresponds to the acquisition of one UWB pulse at the pulse repetition rate of 10 mega pulses per second (Mpps). By using time-interleaved Redundant Signed Digit (RSD) ADCs, the complete ADC occupies only 0.15 mm2 and consumes only 1.4 mW from a 1.8 V power supply. The ADC can be operated in two modes using the same core circuits (operational transconductance amplifier, comparators, etc.). The first mode is the standard RSD doubling mode, while the second mode allows improving the signal-to-noise ratio by adding coherently the transmitted pulses of one symbol. For example, for audio applications, a 300 kbps data rate and processing gain up to 15 dB can be achieved at a clock frequency of 10 MHz.