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conference paper

Composing Relaxed Transactions

Gramoli, Vincent  
•
Guerraoui, Rachid  
•
Letia, Mihai  
2013
Proceedings of the 27th IEEE International Parallel & Distributed Processing Symposium (IPDPS'13)
27th IEEE International Parallel & Distributed Processing Symposium (IPDPS'13)

As the classic transactional abstraction is sometimes considered too restrictive in leveraging parallelism, a lot of work has been devoted to devising relaxed transactional models with the goal of improving concurrency. Nevertheless, the quest for improving concurrency has somehow led to neglect one of the most appealing aspects of transactions: software composition, namely, the ability to develop pieces of software independently and compose them into applications that behave correctly in the face of concurrency. Indeed, a closer look at relaxed transactional models reveals that they do jeopardize composition, raising the fundamental question whether it is at all possible to devise such models while preserving composition. This paper shows that the answer is positive. We present outheritance, a necessary and sufficient condition for a (potentially relaxed) transactional memory to support composition. Basically, outheritance requires child transactions to pass their conflict information to their parent transaction, which in turn maintains this information until commit time. Concrete instantiations of this idea have been used before, classic transactions being the most prevalent example, but we believe to be the first to capture this as a general principle as well as to prove that it is, strictly speaking, equivalent to ensuring composition. We illustrate the benefits of outheritance using elastic trans- actions and show how they can satisfy outheritance and provide composition without hampering concurrency. We leverage this to present a new (transactional) Java package, a composable alternative to the concurrency package of the JDK, and evaluate efficiency through an implementation that speeds up state of the art software transactional memory implementations (TL2, LSA, SwissTM) by almost a factor of 3.

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Type
conference paper
DOI
10.1109/IPDPS.2013.42
Author(s)
Gramoli, Vincent  
Guerraoui, Rachid  
Letia, Mihai  
Date Issued

2013

Publisher

IEEE Computer Society

Published in
Proceedings of the 27th IEEE International Parallel & Distributed Processing Symposium (IPDPS'13)
ISBN of the book

978-0-7695-4971-2

Start page

1171

End page

1182

Subjects

transactional memory

•

multicore processing

•

scalability

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
DCL  
Event nameEvent placeEvent date
27th IEEE International Parallel & Distributed Processing Symposium (IPDPS'13)

Boston, Massachusetts USA

May 20-24, 2013

Available on Infoscience
March 3, 2014
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/101287
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