This paper reports a simulation based study of the non-local tunneling model using a commercially available technology computer-aided design (TCAD) device simulator. Single gate Tunnel FET devices with 400nm gate length based on SOI technology are measured and compared with simulated data. A step by step algorithm to calibrate the nonlocal Band-to-Band tunneling model implemented in Synopsys Sentaurus TCAD has been shown, demonstrating the importance of model parameters. By using only the reduced mass as the fitting parameter we have obtained a physically meaningful fit with the measured data. The dependence of the tunneling generation rate on the different crystallographic directions is also demonstrated for the first time.