We introduce the world’s first SPAD family design in 130 nm SiGe BiCMOS process. At 1.8 µm, we achieved the smallest pitch on record thanks to guard-ring sharing techniques, while keeping a relatively high fill factor of 24.2%. 4×4 SPAD arrays with two parallel selective readout circuits were designed to explore crosstalk and scalability. The SPAD family has a minimum breakdown voltage of 11 V, a maximum PDP of 40.6%, and a typical timing jitter of 47 ps FWHM. The development of silicon SPADs in SiGe process paves the way to Ge-on-Si SPADs for SWIR applications, and to cryogenic optical interfaces for quantum applications.