When designing in Smart Power technologies, TCAD simulations are mandatory to design effective passive protections against parasitic couplings due to minority carriers. The objective of this paper is to propose a spice-based approach to characterize electrical key parameters of a passive protection directly within standard IC design flow avoiding time consuming TCAD simulations. Our methodology consists in integrating a new substrate model in spice to enable designers to derive themselves process specific design rules and reduce substrate couplings. This methodology enables designers to access valuable results in the early stage of IC design, where before such results could be obtained only in the final verification step.